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16 CHAPTER 1. INTRODUCTION TO THE ALLIANCE TOOLS
named mux in and that we want the output pattern file generated by the simulation to be named mux out
(Note that no extension is used with either of the file names used in the command line tools of Alliance). As
noted in this output the behavioral file is compiled, ASIMUT searches for the input pattern file, links the files
and executes them at the intervals indicated in the input pattern file. The design flow up to this point using
ASIMUT is shown in Figure 1.4.
Figure 1.4: Simulating the b e havioral design file using ASIMUT.
We can again open and display the output file mux out.pat with xpat. This time the output signal q also
displays as shown in Figure 1.5. This signal has b ee n derived from the behavioral description of the circuit and
the values assigned to c, a and b. We can check that the multiplexer circuit behaves as expected passing b to
output q when c is 0 and a when c is 1. It is possible also to indicate in the input pattern file if the last values
Figure 1.5: The mux out.pat shown by xpat.
in the simulation must be saved to use them as initial values of the circuit in subsequent simulations. In this
case we just add one line with save; before end; of the input pattern file. Let’s try this using a modified copy
of our previous input pattern file (only the last three lines of muxs in.pat are shown).
<+1 ns> : 10 110 ?*;
<+1 ns> c_a_b : 10 111 ?*;
<+1 ns> : 10 111 ?*;
save;
end;
When using this input pattern file the output of the simulation will be the same, but this time an additional
file named with the same input pattern file name and extension .sav will be generated. Using this .sav file we
can set the initial conditions of a circuit before running the simulation with any other input pattern file.
The options in ASIMUT are shown in Table 1.1. The .ext extension is the extension specified by the
environment variable VH
DLYSFX. We can check its value as follows.
% env | grep VH
VH_MAXERR=10
VH_BEHSFX=vbe
VH_PATSFX=pat
VH_DLYSFX=dly
- Contents 3
- 4 CONTENTS 4
- List of Figures 5
- 6 LIST OF FIGURES 6
- List of Tables 7
- 8 LIST OF TABLES 8
- 10 LIST OF TABLES 10
- Chapter 1 11
- 1.1. ASIMUT 15 15
- 1.1. ASIMUT 19 19
- 1.3 BOOG 26
- 1.4 BOOM 26
- 1.5 COUGAR 29
- 1.5. COUGAR 31 31
- 1.5. COUGAR 33 33
- 1.6 DREAL 34
- 1.7 DRUC 36
- 1.8 FlatBeh 37
- 1.9 FLATLO 39
- 1.10 FLATPH 39
- 1.11 FMI 39
- 1.12 FSP 41
- 1.13 GENPAT 41
- 1.14 GRAAL 43
- 1.15 K2F 43
- 1.16 L2P 44
- Figure 1.18 46
- 1.17 LOON 47
- 1.18 LVX 48
- 1.19 MOKA 48
- 1.20 NERO 49
- 1.21 OCP 50
- 1.22 Proof 51
- 1.23 Ring 53
- 1.24 S2R 53
- 1.25 SCAPIN 53
- 1.26 SYF 54
- 1.27 VASY 55
- 1.28 X2Y 55
- 1.29 XFSM 56
- 1.30 XPAT 56
- 1.31 XSCH 57
- 1.32 XVPN 57
- Combinational Design Examples 59
- (a) (b) (c) 60
- 2.1.3 Adder Tree 64
- 2.1.4 Output Adder 66
- 2.1.5 4-bit Multiplier 67
- And set a few new ones 83
- Bibliography 87
Philips FW-C717/22 manuali
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